290 search results - page 2 / 58 » Timing analysis in high-level synthesis |
IPPS
2007
IEEE
14 years 1 days ago
2007
IEEE
DATE
2008
IEEE
14 years 6 days ago
2008
IEEE
— The worst-case delay/power of function units has been used in traditional high level synthesis to facilitate design space exploration. As technology scales to nanometer regime,...
CORR
2006
Springer
13 years 5 months ago
2006
Springer
We introduce a new approach to take into account the memory architecture and the memory mapping in the High- Level Synthesis of Real-Time embedded systems. We formalize the memory...
ISQED
2007
IEEE
14 years 19 hour ago
2007
IEEE
In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced schedulin...
DATE
2002
IEEE
13 years 10 months ago
2002
IEEE
Optimizing power consumption at high-level is a critical step towards power-efficient digital system designs. This paper addresses the power management problem by scheduling a giv...