118 search results - page 3 / 24 » Timing constraint specification and synthesis in behavioral ... |
ISSS
2000
IEEE
13 years 10 months ago
2000
IEEE
This paper concerns automatic hardware synthesis from data flow graph (DFG) specification in system level design. In the presented design methodology, each node of a data flow gra...
TCAD
1998
13 years 5 months ago
1998
— We introduce a transformation, named rephasing, that manipulates the timing parameters in control-data-flow graphs (CDFG’s) during the high-level synthesis of data-pathinten...
ICCAD
1994
IEEE
13 years 10 months ago
1994
IEEE
We present in this paper a novel control synthesis technique for system-level specifications that are better described as a set of concurrent synchronous descriptions, their synch...
DAC
1999
ACM
13 years 10 months ago
1999
ACM
This paper presents a novel approach for synthesis of analog systems from behavioral VHDL-AMS specifications. We implemented this approach in the VASE behavioral-synthesis tool. ...
SPIN
2000
Springer
13 years 9 months ago
2000
Springer
The Temporal Rover is a specification based verification tool for applications written in C, C++, Java, Verilog and VHDL. The tool combines formal specification, using Linear-Time ...