16 search results - page 2 / 4 » Timing driven placement in interaction with netlist transfor... |
ISPD
2009
ACM
14 years 4 days ago
2009
ACM
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignmen...
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
In a realistic design flow, circuit and system optimizations must interact with physical aspects of the design. For example, improvements in timing and power may require replacing ...
DATE
2005
IEEE
13 years 11 months ago
2005
IEEE
In this paper, we present an experimental integrated platform for the research, development and evaluation of new VLSI back-end algorithms and design flows. Interconnect scaling ...
ICCAD
2004
IEEE
14 years 2 months ago
2004
IEEE
—In this paper, we present a new block budgeting algorithm which speeds up timing closure in timing driven hierarchical flows. After a brief description of the addressed flow, ...
ICCAD
2001
IEEE
14 years 2 months ago
2001
IEEE
In this paper, we present novel algorithms that effectively combine physical layout and early logic synthesis to improve overall design quality. In addition, we employ partitionin...