4164 search results - page 3 / 833 » Timing model reduction for hierarchical timing analysis |
CONCUR
1999
Springer
13 years 10 months ago
1999
Springer
Abstract. The paper presents a partial order reduction method applicable to networks of timed automata. The advantage of the method is that it reduces both the number of explored c...
FPGA
1998
ACM
13 years 10 months ago
1998
ACM
The goal of this paper is to perform a timing optimization of a circuit described by a network of cells on a target structure whose connection delays have discrete values following...
WSC
1998
1998
Effective Implementation of Cycle Time Reduction Strategies for Semiconductor Back-end Manufacturing
13 years 7 months ago
Using discrete-event simulation models, a study was conducted to evaluate the current production practices of a high-volume semiconductor back-end operation. The overall goal was ...
SIGADA
2007
Springer
13 years 12 months ago
2007
Springer
A system based on a hierarchical scheduler is a system in which the processor is shared between several collaborative schedulers. Such schedulers exist since 1960 and they are bec...
ATVA
2004
Springer
13 years 11 months ago
2004
Springer
This paper proposes a partial order reduction algorithm for timed trace theoretic verification in order to detect both safety failures and timing failures of timed circuits effic...