4 search results - page 1 / 1 » Timing optimization via nest-loop pipelining considering cod... |
MAM
2008
13 years 4 months ago
2008
MAM
2006
13 years 4 months ago
2006
The increasingly complicated DSP processors and applications with strict timing and code size constraints require design automation tools to consider multiple optimizations such a...
EUROPAR
2010
Springer
13 years 5 months ago
2010
Springer
Abstract. Limited bandwidth to off-chip main memory is a performance bottleneck in chip multiprocessors for streaming computations, such as Cell/B.E., and this will become even mor...
FCCM
2007
IEEE
13 years 6 months ago
2007
IEEE
Creating a high throughput sparse matrix vector multiplication (SpMxV) implementation depends on a balanced system design. In this paper, we introduce the innovative SpMxV Solver ...