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ICCAD
2005
IEEE
114views Hardware» more  ICCAD 2005»
14 years 1 months ago
Statistical timing analysis with two-sided constraints
Based on a timing yield model, a statistical static timing analysis technique is proposed. This technique preserves existing methodology by selecting a “device file setting” ...
Khaled R. Heloue, Farid N. Najm
DATE
2010
IEEE
171views Hardware» more  DATE 2010»
13 years 10 months ago
Statistical static timing analysis using Markov chain Monte Carlo
—We present a new technique for statistical static timing analysis (SSTA) based on Markov chain Monte Carlo (MCMC), that allows fast and accurate estimation of the right-hand tai...
Yashodhan Kanoria, Subhasish Mitra, Andrea Montana...
ICCAD
2005
IEEE
133views Hardware» more  ICCAD 2005»
14 years 1 months ago
Gate sizing using incremental parameterized statistical timing analysis
— As technology scales into the sub-90nm domain, manufacturing variations become an increasingly significant portion of circuit delay. As a result, delays must be modeled as sta...
Matthew R. Guthaus, Natesan Venkateswaran, Chandu ...
DAC
2005
ACM
14 years 5 months ago
An efficient algorithm for statistical minimization of total power under timing yield constraints
Power minimization under variability is formulated as a rigorous statistical robust optimization program with a guarantee of power and timing yields. Both power and timing metrics...
Murari Mani, Anirudh Devgan, Michael Orshansky
FPGA
2007
ACM
142views FPGA» more  FPGA 2007»
13 years 11 months ago
Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis
Variations in the semiconductor fabrication process results in variability in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. The re...
N. Pete Sedcole, Peter Y. K. Cheung