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» Tolerating Hard Faults in Microprocessor Array Structures
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COMPSAC
1998
IEEE
13 years 10 months ago
Architecture of ROAFTS/Solaris: A Solaris-Based Middleware for Real-Time Object-Oriented Adaptive Fault Tolerance Support
Middleware implementation of various critical services required by large-scale and complex real-time applications on top of COTS operating system is currently an approach of growi...
Eltefaat Shokri, Patrick Crane, K. H. Kim, Chittur...
GLOBECOM
2007
IEEE
14 years 4 days ago
Redundant Array of Independent Fabrics - An Architecture for Next Generation Network
As the next generation network begins to incorporate the Internet, telecommunication and TV services, it becomes one of the most critical infrastructures for our society. Routers c...
Rongsen He, José G. Delgado-Frias
ISCA
2007
IEEE
130views Hardware» more  ISCA 2007»
14 years 2 days ago
Dynamic prediction of architectural vulnerability from microarchitectural state
Transient faults due to particle strikes are a key challenge in microprocessor design. Driven by exponentially increasing transistor counts, per-chip faults are a growing burden. ...
Kristen R. Walcott, Greg Humphreys, Sudhanva Gurum...
ISCA
2007
IEEE
120views Hardware» more  ISCA 2007»
14 years 2 days ago
Examining ACE analysis reliability estimates using fault-injection
ACE analysis is a technique to provide an early reliability estimate for microprocessors. ACE analysis couples data from performance models with low level design details to identi...
Nicholas J. Wang, Aqeel Mahesri, Sanjay J. Patel
SRDS
2008
IEEE
14 years 5 days ago
Self-Stabilization in Tree-Structured Peer-to-Peer Service Discovery Systems
The efficiency of service discovery is critical in the development of fully decentralized middleware intended to manage large scale computational grids. This demand influenced t...
Eddy Caron, Ajoy Kumar Datta, Franck Petit, C&eacu...