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» Tolerating node failures in cache only memory architectures
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CODES
2009
IEEE
13 years 9 months ago
TotalProf: a fast and accurate retargetable source code profiler
Profilers play an important role in software/hardware design, optimization, and verification. Various approaches have been proposed to implement profilers. The most widespread app...
Lei Gao, Jia Huang, Jianjiang Ceng, Rainer Leupers...
BROADNETS
2005
IEEE
13 years 11 months ago
A Lightweight framework for source-to-sink data transfer in wireless sensor networks
— Lightweight protocols that are both bandwidth and power thrifty are desirable for sensor networks. In addition, for many sensor network applications, timeliness of data deliver...
James Jobin, Zhenqiang Ye, Honomount Rawat, Srikan...
ASPLOS
2006
ACM
13 years 11 months ago
Ultra low-cost defect protection for microprocessor pipelines
The sustained push toward smaller and smaller technology sizes has reached a point where device reliability has moved to the forefront of concerns for next-generation designs. Sil...
Smitha Shyam, Kypros Constantinides, Sujay Phadke,...
HPCA
2004
IEEE
14 years 5 months ago
Out-of-Order Commit Processors
Modern out-of-order processors tolerate long latency memory operations by supporting a large number of inflight instructions. This is particularly useful in numerical applications...
Adrián Cristal, Daniel Ortega, Josep Llosa,...