1541 search results - page 2 / 309 » Tools and Techniques for Model Checking Networked Programs |
TCAD
2008
13 years 5 months ago
2008
The quality and the correctness of software is often the greatest concern in electronic systems. Formal verification tools can provide a guarantee that a design is free of specific...
SIGSOFT
2007
ACM
14 years 6 months ago
2007
ACM
Automated verification is a technique for establishing if certain properties, usually expressed in temporal logic, hold for a system model. The model can be defined using a high-l...
CORR
2008
Springer
13 years 5 months ago
2008
Springer
Requirements about the quality of clinical guidelines can be represented by schemata borrowed from the theory of abductive diagnosis, using temporal logic to model the time-orient...
APSEC
1999
IEEE
13 years 9 months ago
1999
IEEE
For the practical development of provably correct software for embedded systems the close integration of CASE tools and verification tools is required. This paper describes the co...
JSC
2010
13 years 2 days ago
2010
A uniform verification problem for parameterized systems is to determine whether a temporal property is satisfied for every instance of the system which is composed of an arbitrar...