115 search results - page 23 / 23 » Topological Design of Interconnected LAN-MAN Networks |
CAL
2007
13 years 4 months ago
2007
—The design of scalable and reliable interconnection networks for multicore chips (NoCs) introduces new design constraints like power consumption, area, and ultra low latencies. ...
DATE
2004
IEEE
13 years 8 months ago
2004
IEEE
Latency-insensitive systems were recently proposed by Carloni et al. as a correct-by-construction methodology for single-clock system-on-a-chip (SoC) design using predesigned IP b...
ACSC
2003
IEEE
13 years 10 months ago
2003
IEEE
Clusters of commodity machines have become a popular way of building cheap high performance parallel computers. Many of these designs rely on standard Ethernet networks as a syste...
JSA
2007
13 years 4 months ago
2007
Multiprocessor system-on-chip (MP-SoC) platforms represent an emerging trend for embedded multimedia applications. To enable MP-SoC platforms, scalable communication-centric inter...
IWVF
2001
Springer
13 years 9 months ago
2001
Springer
Volumetric images of small mortar samples under load are acquired by X-ray microtomography. The images are binarized at many different threshold values, and over a million connecte...