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» Topologically constrained logic synthesis
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ISPD
2003
ACM
88views Hardware» more  ISPD 2003»
13 years 11 months ago
Porosity aware buffered steiner tree construction
— In order to achieve timing closure on increasingly complex IC designs, buffer insertion needs to be performed on thousands of nets within an integrated physical synthesis syste...
Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jia...
DATE
1999
IEEE
123views Hardware» more  DATE 1999»
13 years 10 months ago
An Algorithm for Face-Constrained Encoding of Symbols Using Minimum Code Length
Different logic synthesis tasks have been formulated as input encoding problems but restricted to use a minimum number of binary variables. This paper presents an original column ...
Manuel Martínez, Maria J. Avedillo, Jos&eac...
ISPD
1999
ACM
128views Hardware» more  ISPD 1999»
13 years 10 months ago
Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis
There is an increasing need in modern VLSI designs for circuits implemented in high-performance logic families such as Cascode Voltage Switch Logic, Pass Transistor Logic, and dom...
Michael A. Riepe, Karem A. Sakallah
DATE
2000
IEEE
82views Hardware» more  DATE 2000»
13 years 10 months ago
Constructive Library-Aware Synthesis Using Symmetries
In this paper a constructive library-aware multilevel logic synthesis approach using symmetries is described. It integrates the technology-independent and technologydependent stag...
Victor N. Kravets, Karem A. Sakallah
DAC
2003
ACM
14 years 6 months ago
The synthesis of cyclic combinational circuits
Combinational circuits are generally thought of as acyclic structures. It is known that cyclic structures can be combinational, and techniques have been proposed to analyze cyclic...
Marc D. Riedel, Jehoshua Bruck