Sciweavers

133 search results - page 26 / 27
» Towards Nanoelectronics Processor Architectures
Sort
View
HPCA
2009
IEEE
14 years 5 months ago
Dacota: Post-silicon validation of the memory subsystem in multi-core designs
The number of functional errors escaping design verification and being released into final silicon is growing, due to the increasing complexity and shrinking production schedules ...
Andrew DeOrio, Ilya Wagner, Valeria Bertacco
HPDC
2008
IEEE
13 years 11 months ago
StoreGPU: exploiting graphics processing units to accelerate distributed storage systems
Today Graphics Processing Units (GPUs) are a largely underexploited resource on existing desktops and a possible costeffective enhancement to high-performance systems. To date, mo...
Samer Al-Kiswany, Abdullah Gharaibeh, Elizeu Santo...
MICRO
2007
IEEE
168views Hardware» more  MICRO 2007»
13 years 11 months ago
Global Multi-Threaded Instruction Scheduling
Recently, the microprocessor industry has moved toward chip multiprocessor (CMP) designs as a means of utilizing the increasing transistor counts in the face of physical and micro...
Guilherme Ottoni, David I. August
ASPLOS
2006
ACM
13 years 11 months ago
Ultra low-cost defect protection for microprocessor pipelines
The sustained push toward smaller and smaller technology sizes has reached a point where device reliability has moved to the forefront of concerns for next-generation designs. Sil...
Smitha Shyam, Kypros Constantinides, Sujay Phadke,...
ICS
2005
Tsinghua U.
13 years 10 months ago
Disk layout optimization for reducing energy consumption
Excessive power consumption is becoming a major barrier to extracting the maximum performance from high-performance parallel systems. Therefore, techniques oriented towards reduci...
Seung Woo Son, Guangyu Chen, Mahmut T. Kandemir