Sciweavers

10 search results - page 1 / 2
» Towards an Asynchronous MIPS Processor
Sort
View
APCSAC
2003
IEEE
13 years 10 months ago
Towards an Asynchronous MIPS Processor
Qianyi Zhang, Georgios K. Theodoropoulos
ICCD
2000
IEEE
96views Hardware» more  ICCD 2000»
13 years 9 months ago
AMULET3: A 100 MIPS Asynchronous Embedded Processor
AMULET3 is a 32-bit asynchronous processor core that is fully instruction set compatible with the clocked ARM cores. It represents the culmination of ten years of research and dev...
Stephen B. Furber, David A. Edwards, Jim D. Garsid...
DATE
2005
IEEE
110views Hardware» more  DATE 2005»
13 years 10 months ago
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture
The increasing complexity and the short life cycles of embedded systems are pushing the current system-onchip designs towards a rapid increasing on the number of programmable proc...
Alexandre M. Amory, Marcelo Lubaszewski, Fernando ...
DATE
2010
IEEE
124views Hardware» more  DATE 2010»
13 years 9 months ago
Control network generator for latency insensitive designs
—Creating latency insensitive or asynchronous designs from clocked designs has potential benefits of increased modularity and robustness to variations. Several transformations h...
Eliyah Kilada, Kenneth S. Stevens
TACAS
2010
Springer
210views Algorithms» more  TACAS 2010»
13 years 11 months ago
Automatic Analysis of Scratch-Pad Memory Code for Heterogeneous Multicore Processors
Modern multicore processors, such as the Cell Broadband Engine, achieve high performance by equipping accelerator cores with small “scratchpad” memories. The price for increase...
Alastair F. Donaldson, Daniel Kroening, Philipp R&...