44 search results - page 8 / 9 » Trace-Level Speculative Multithreaded Architecture |
ISCA
2009
IEEE
14 years 12 days ago
2009
IEEE
Industry has shifted towards multi-core designs as we have hit the memory and power walls. However, single thread performance remains of paramount importance since some applicatio...
HPCA
2008
IEEE
14 years 6 months ago
2008
IEEE
In this paper, we propose Runahead Threads (RaT) as a valuable solution for both reducing resource contention and exploiting memory-level parallelism in Simultaneous Multithreaded...
DATE
2010
IEEE
13 years 11 months ago
2010
IEEE
—This paper presents a design space exploration of a selective load value prediction scheme suitable for energyaware Simultaneous Multi-Threaded (SMT) architectures. A load value...
HPCA
1999
IEEE
13 years 10 months ago
1999
IEEE
Processors that can simultaneously execute multiple paths of execution will only exacerbate the fetch bandwidth problem already plaguing conventional processors. On a multiple-pat...
APCSAC
2000
IEEE
13 years 10 months ago
2000
IEEE
This paper briefly reviews the current research into RISC microprocessor architecture, which now seems to be so complex as to make the acronym somewhat of an oxymoron. In response...