14 search results - page 1 / 3 » Tradeoff between data-, instruction-, and thread-level paral... |
ICS
2007
Tsinghua U.
13 years 11 months ago
2007
Tsinghua U.
This paper explores the scalability of the Stream Processor architecture along the instruction-, data-, and thread-level parallelism dimensions. We develop detailed VLSI-cost and ...
ICMCS
2006
IEEE
13 years 10 months ago
2006
IEEE
The MISP Processor is a programmable media processor which supports multi-issuing, multi-threading and stream processing techniques. MISP executes applications that have been mapp...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
Efficient use of the memory hierarchy is critical for achieving high performance in a multiprocessor systemon-chip. An external memory that is shared between processors is a bottl...
FPGA
2004
ACM
13 years 10 months ago
2004
ACM
The speedup over a microprocessor that can be achieved by implementing some programs on an FPGA has been extensively reported. This paper presents an analysis, both quantitative a...
ICCD
2001
IEEE
14 years 1 months ago
2001
IEEE
General-purpose microprocessors augmented with SIMD execution units enhance multimedia applications by exploiting data level parallelism. However, supporting/overhead related inst...