372 search results - page 2 / 75 » Transaction Based Modeling and Verification of Hardware Prot... |
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
CHARME
2001
Springer
13 years 8 months ago
2001
Springer
We consider the formal verification of the cache coherence protocol of the Stanford FLASH multiprocessor for N processors. The proof uses the SMV proof assistant, a proof system ba...
ACSC
2009
IEEE
13 years 8 months ago
2009
IEEE
The Session Initiation Protocol (SIP) is one of the leading protocols for multimedia control over the Internet, including initiating, maintaining and terminating multimedia sessio...
DSD
2009
IEEE
13 years 2 months ago
2009
IEEE
Several traditional VHDL fault injection mechanisms like mutants or saboteurs have been adapted to SystemC model descriptions. The main drawback of these approaches is the necessi...
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
—The need to have Transaction Level models early in the design cycle is becoming more and more important to shorten the development times of complex Systems-on-Chip (SoC). These ...