264 search results - page 2 / 53 » Transaction level modeling: an overview |
ASPDAC
2009
ACM
13 years 10 months ago
2009
ACM
— This paper proposes the first automatic approach to simultaneously generate Cycle Accurate and Cycle Count Accurate transaction level bus models. Since TLM (Transaction Level M...
DAC
2006
ACM
13 years 11 months ago
2006
ACM
This paper describes how systems companies are adopting SystemC transaction level models for system on chip design and verification, and how these transaction level models are bei...
ASPLOS
2006
ACM
13 years 11 months ago
2006
ACM
Exploiting thread level parallelism is paramount in the multi-core era. Transactions enable programmers to expose such parallelism by greatly simplifying the multi-threaded progra...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
Most of the challenges related to the development of multi-processor platforms for complex wireless and multimedia applications fall into the Electronic System Level (ESL) domain....
CODES
2005
IEEE
13 years 11 months ago
2005
IEEE
Majority of existing works on system level power estimation have focused on the processor, while there are very few that address power consumption of peripherals in a SoC. With th...