Sciweavers

19 search results - page 3 / 4
» Transient Fault Tolerant QDI Interconnects Using Redundant C...
Sort
View
VLSID
2004
IEEE
117views VLSI» more  VLSID 2004»
14 years 6 months ago
Evaluating the Reliability of Defect-Tolerant Architectures for Nanotechnology with Probabilistic Model Checking
As we move from deep submicron technology to nanotechnology for device manufacture, the need for defect-tolerant architectures is gaining importance. This is because, at the nanos...
Gethin Norman, David Parker, Marta Z. Kwiatkowska,...
CODES
2011
IEEE
12 years 5 months ago
Analysis and optimization of fault-tolerant task scheduling on multiprocessor embedded systems
Reliability is a major requirement for most safety-related systems. To meet this requirement, fault-tolerant techniques such as hardware replication and software re-execution are ...
Jia Huang, Jan Olaf Blech, Andreas Raabe, Christia...
ET
2008
92views more  ET 2008»
13 years 5 months ago
Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs
Processor cores embedded in systems-on-a-chip (SoCs) are often deployed in critical computations, and when affected by faults they may produce dramatic effects. When hardware harde...
Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa...
CORR
2010
Springer
94views Education» more  CORR 2010»
13 years 5 months ago
Unidirectional Error Correcting Codes for Memory Systems: A Comparative Study
In order to achieve fault tolerance, highly reliable system often require the ability to detect errors as soon as they occur and prevent the speared of erroneous information throu...
Muzhir Al-Ani, Qeethara Al-Shayea
IEEEPACT
2006
IEEE
13 years 11 months ago
Self-checking instructions: reducing instruction redundancy for concurrent error detection
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
Sumeet Kumar, Aneesh Aggarwal