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» Transient Power Management Through High Level Synthesis
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CGO
2005
IEEE
13 years 11 months ago
SWIFT: Software Implemented Fault Tolerance
To improve performance and reduce power, processor designers employ advances that shrink feature sizes, lower voltage levels, reduce noise margins, and increase clock rates. Howev...
George A. Reis, Jonathan Chang, Neil Vachharajani,...
VLSID
2006
IEEE
192views VLSI» more  VLSID 2006»
13 years 11 months ago
Beyond RTL: Advanced Digital System Design
This tutorial focuses on advanced techniques to cope with the complexity of designing modern digital chips which are complete systems often containing multiple processors, complex...
Shiv Tasker, Rishiyur S. Nikhil
ECBS
1996
IEEE
155views Hardware» more  ECBS 1996»
13 years 9 months ago
Model-Integrated Program Synthesis Environment
In this paper, it is shown that, through the use of Model-Integrated Program Synthesis MIPS, parallel real-time implementations of image processing data ows can be synthesized fro...
Janos Sztipanovits, Gabor Karsai, Hubertus Franke
AADEBUG
2005
Springer
13 years 11 months ago
An integrated debugging environment for reprogrammble hardware systems
Reprogrammable hardware systems are traditionally very difficult to debug due to their high level of parallelism. In our solution to this problem, features are inserted into the u...
Kevin Camera, Hayden Kwok-Hay So, Robert W. Broder...
PPDP
2010
Springer
13 years 4 months ago
Graph queries through datalog optimizations
This paperdescribes the use of a powerful graph query language for querying programs, and a novel combination of transformations for generating efficient implementations of the q...
K. Tuncay Tekle, Michael Gorbovitski, Yanhong A. L...