2 search results - page 1 / 1 » Transition Maximization Techniques for Enhancing the Two-Pat... |
VTS
1998
IEEE
13 years 9 months ago
1998
IEEE
This paper presents simulation evidence supporting the use of bit transition maximization techniques in the design of hardware test pattern generators TPGs. Bit transition maximiz...
VTS
2002
IEEE
13 years 10 months ago
2002
IEEE
We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition pr...