2 search results - page 1 / 1 » Transition-activity aware design of reduction-stages for par... |
GLVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
We propose an interconnect reorganization algorithm for reduction stages in parallel multipliers. It aims at minimizing power consumption for given static probabilities at the pri...
DCOSS
2006
Springer
13 years 8 months ago
2006
Springer
We develop algorithms for finding the minimum energy transmission schedule for duty-cycle and rate constrained wireless sensor nodes transmitting over an interference channel. Sinc...