7 search results - page 1 / 2 » Transparent Memory Testing for Pattern-Sensitive Faults |
ITC
1994
IEEE
13 years 9 months ago
1994
IEEE
DDECS
2009
IEEE
13 years 9 months ago
2009
IEEE
Although the Neighborhood Pattern Sensitive Fault (NPSF) model is recognized as a high quality fault model for memory arrays, the excessive test application time cost associated wi...
VLSID
2001
IEEE
14 years 5 months ago
2001
IEEE
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...
ET
2008
13 years 4 months ago
2008
Processor cores embedded in systems-on-a-chip (SoCs) are often deployed in critical computations, and when affected by faults they may produce dramatic effects. When hardware harde...
EDCC
1999
Springer
13 years 9 months ago
1999
Springer
Abstract. The paper presents a new approach to transparent BIST for wordoriented RAMs which is based on the transformation of March transparent test algorithms to the symmetric ver...