9 search results - page 2 / 2 » Trends of On-Chip Interconnects in Deep Sub-Micron VLSI |
ICCAD
2006
IEEE
14 years 2 months ago
2006
IEEE
With shrinking feature size and growing integration density in the Deep Sub-Micron technologies, the global buses are fast becoming the “weakest-links” in VLSI design. They ha...
ICCAD
1997
IEEE
13 years 9 months ago
1997
IEEE
Interconnect has become the dominating factor in determining circuit performance and reliability in deep submicron designs. In this embedded tutorial, we first discuss the trends...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
Interconnection networks in Systems-On-Chip begin to have a non-negligible impact on the power consumption of a whole system. This is because of increasing inter-wire capacitances...
DSD
2002
IEEE
13 years 10 months ago
2002
IEEE
Continuing VLSI technology scaling raises several deep submicron (DSM) problems like relatively slow interconnect, power dissipation and distribution, and signal integrity. Those ...