55 search results - page 10 / 11 » Tuning of Loop Cache Architectures to Programs in Embedded S... |
NOCS
2007
IEEE
13 years 11 months ago
2007
IEEE
The paper introduces Network-on-Chip (NoC) design methodology and low cost mechanisms for supporting efficient cache access and cache coherency in future high-performance Chip Mul...
LCTRTS
2005
Springer
13 years 10 months ago
2005
Springer
Software pipelining is a critical optimization for producing efficient code for VLIW/EPIC and superscalar processors in highperformance embedded applications such as digital sign...
SENSYS
2009
ACM
14 years 4 days ago
2009
ACM
This paper describes Mercury, a wearable, wireless sensor platform for motion analysis of patients being treated for neuromotor disorders, such as Parkinson’s Disease, epilepsy,...
CASES
2007
ACM
13 years 9 months ago
2007
ACM
In this paper we describe the design and implementation of a flexible, and extensible, just-in-time ARM simulator designed to run co-operatively with a multi-core DSP simulator on...
CASES
2003
ACM
13 years 10 months ago
2003
ACM
Knowing the Worst-Case Execution Time (WCET) of a program is necessary when designing and verifying real-time systems. A correct WCET analysis method must take into account the po...