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ISCA
2000
IEEE
111views Hardware» more  ISCA 2000»
13 years 9 months ago
Understanding the backward slices of performance degrading instructions
For many applications, branch mispredictions and cache misses limit a processor’s performance to a level well below its peak instruction throughput. A small fraction of static i...
Craig B. Zilles, Gurindar S. Sohi
ASPLOS
2006
ACM
13 years 8 months ago
SlicK: slice-based locality exploitation for efficient redundant multithreading
Transient faults are expected a be a major design consideration in future microprocessors. Recent proposals for transient fault detection in processor cores have revolved around t...
Angshuman Parashar, Anand Sivasubramaniam, Sudhanv...
SIGSOFT
1995
ACM
13 years 8 months ago
Precise Interprocedural Chopping
The notion of a program slice, originally introduced by Mark Weiser, is a fundamental operation for addressing many software-engineering problems, including program understanding,...
Thomas W. Reps, Genevieve Rosay
IISWC
2008
IEEE
13 years 11 months ago
Evaluating the impact of dynamic binary translation systems on hardware cache performance
Dynamic binary translation systems enable a wide range of applications such as program instrumentation, optimization, and security. DBTs use a software code cache to store previou...
Arkaitz Ruiz-Alvarez, Kim M. Hazelwood
TVLSI
2010
12 years 11 months ago
C-Pack: A High-Performance Microprocessor Cache Compression Algorithm
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
Xi Chen, Lei Yang, Robert P. Dick, Li Shang, Haris...