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MICRO
2010
IEEE
140views Hardware» more  MICRO 2010»
13 years 3 months ago
STEM: Spatiotemporal Management of Capacity for Intra-core Last Level Caches
Efficient management of last level caches (LLCs) plays an important role in bridging the performance gap between processor cores and main memory. This paper is motivated by two key...
Dongyuan Zhan, Hong Jiang, Sharad C. Seth
TMI
2011
127views more  TMI 2011»
13 years 7 days ago
Reconstruction of Large, Irregularly Sampled Multidimensional Images. A Tensor-Based Approach
Abstract—Many practical applications require the reconstruction of images from irregularly sampled data. The spline formalism offers an attractive framework for solving this prob...
Oleksii Vyacheslav Morozov, Michael Unser, Patrick...
ICFP
2012
ACM
11 years 7 months ago
Nested data-parallelism on the gpu
Graphics processing units (GPUs) provide both memory bandwidth and arithmetic performance far greater than that available on CPUs but, because of their Single-Instruction-Multiple...
Lars Bergstrom, John H. Reppy
ISCA
2005
IEEE
90views Hardware» more  ISCA 2005»
13 years 11 months ago
Optimizing Replication, Communication, and Capacity Allocation in CMPs
Chip multiprocessors (CMPs) substantially increase capacity pressure on the on-chip memory hierarchy while requiring fast access. Neither private nor shared caches can provide bot...
Zeshan Chishti, Michael D. Powell, T. N. Vijaykuma...
NOCS
2007
IEEE
13 years 11 months ago
The Power of Priority: NoC Based Distributed Cache Coherency
The paper introduces Network-on-Chip (NoC) design methodology and low cost mechanisms for supporting efficient cache access and cache coherency in future high-performance Chip Mul...
Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginos...