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» Using Decision Diagrams to Design ULMs for FPGAs
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JSAT
2006
126views more  JSAT 2006»
13 years 5 months ago
Complexity Results for Quantified Boolean Formulae Based on Complete Propositional Languages
Several propositional fragments have been considered so far as target languages for knowledge compilation and used for improving computational tasks from major AI areas (like infe...
Sylvie Coste-Marquis, Daniel Le Berre, Florian Let...
CLEIEJ
2002
192views more  CLEIEJ 2002»
13 years 5 months ago
Automatic ObjectPascal Code Generation from Catalysis Specifications
This paper presents a Component-based Framework Development Process, of the Cardiology Domain. The Framework, called FrameCardio, was developed in 4 steps: 1Problem Domain Definit...
João Luís Cardoso de Moraes, Ant&oci...
ISMVL
2009
IEEE
124views Hardware» more  ISMVL 2009»
14 years 3 days ago
Equivalence Checking of Reversible Circuits
Determining the equivalence of reversible circuits designed to meet a common specification is considered. The circuits’ primary inputs and outputs must be in pure logic states ...
Robert Wille, Daniel Große, D. Michael Mille...
DAC
2004
ACM
13 years 9 months ago
Implicit pseudo boolean enumeration algorithms for input vector control
In a CMOS combinational logic circuit, the subthreshold leakage current in the standby state depends on the state of the inputs. In this paper we present a new approach to identif...
Kaviraj Chopra, Sarma B. K. Vrudhula
FPGA
2009
ACM
159views FPGA» more  FPGA 2009»
14 years 7 days ago
Choose-your-own-adventure routing: lightweight load-time defect avoidance
Aggressive scaling increases the number of devices we can integrate per square millimeter but makes it increasingly difficult to guarantee that each device fabricated has the inte...
Raphael Rubin, André DeHon