33 search results - page 4 / 7 » Using Dynamic Binary Translation to Fuse Dependent Instructi... |
ERSA
2009
13 years 3 months ago
2009
In this paper, we introduce the Woolcano reconfigurable processor architecture. The architecture is based on the Xilinx Virtex-4 FX FPGA and leverages the Auxiliary Processing Uni...
IEEEPACT
2007
IEEE
14 years 3 days ago
2007
IEEE
Continued scaling of CMOS technology to smaller transistor sizes makes modern processors more susceptible to both transient and permanent hardware faults. Circuitlevel techniques ...
CGO
2003
IEEE
13 years 11 months ago
2003
IEEE
Software dynamic translation (SDT) is a technology that permits the modification of an executing program’s instructions. In recent years, SDT has received increased attention, f...
CGO
2006
IEEE
13 years 12 months ago
2006
IEEE
As the amount of available silicon resources on one chip increases, we have seen the advent of ever increasing parallel resources integrated on-chip. Many architectures use these ...
ISCA
2008
IEEE
14 years 6 days ago
2008
IEEE
Performance improvement solely through transistor scaling is becoming more and more difficult, thus it is increasingly common to see domain specific accelerators used in conjunc...