Sciweavers

111 search results - page 1 / 23
» Using Multiple Memory Access Instructions for Reducing Code ...
Sort
View
CC
2004
Springer
13 years 9 months ago
Using Multiple Memory Access Instructions for Reducing Code Size
An important issue in embedded systems design is the size of programs. As computing devices decrease in size, yet with more and more functions, better code size optimizations are i...
Neil Johnson, Alan Mycroft
CC
2003
Springer
192views System Software» more  CC 2003»
13 years 9 months ago
Address Register Assignment for Reducing Code Size
Abstract. In DSP processors, minimizing the amount of address calculations is critical for reducing code size and improving performance since studies of programs have shown that in...
Mahmut T. Kandemir, Mary Jane Irwin, Guilin Chen, ...
ACMMSP
2004
ACM
92views Hardware» more  ACMMSP 2004»
13 years 9 months ago
Instruction combining for coalescing memory accesses using global code motion
Instruction combining is an optimization to replace a sequence of instructions with a more efficient instruction yielding the same result in a fewer machine cycles. When we use it...
Motohiro Kawahito, Hideaki Komatsu, Toshio Nakatan...
CASES
2003
ACM
13 years 9 months ago
Reducing code size with echo instructions
In an embedded system, the cost of storing a program onchip can be as high as the cost of a microprocessor. Compressing an application’s code to reduce the amount of memory requ...
Jeremy Lau, Stefan Schoenmackers, Timothy Sherwood...
HPCA
2005
IEEE
14 years 4 months ago
Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
Aamer Jaleel, Bruce L. Jacob