111 search results - page 21 / 23 » Using Multiple Memory Access Instructions for Reducing Code ... |
FPL
2009
Springer
13 years 10 months ago
2009
Springer
Run-time Partial Reconfiguration (PR) speed is significant in applications especially when fast IP core switching is required. In this paper, we propose to use Direct Memory Acce...
ICS
1999
Tsinghua U.
13 years 10 months ago
1999
Tsinghua U.
This paper presents a technique, adaptive replication, for automatically eliminating synchronization bottlenecks in multithreaded programs that perform atomic operations on object...
IJHPCA
2010
13 years 4 months ago
2010
Sparse matrix operations achieve only small fractions of peak CPU speeds because of the use of specialized, indexbased matrix representations, which degrade cache utilization by i...
CCS
2005
ACM
13 years 11 months ago
2005
ACM
Human-memorable passwords are a mainstay of computer security. To decrease vulnerability of passwords to bruteforce dictionary attacks, many organizations enforce complicated pass...
ICS
2009
Tsinghua U.
14 years 16 days ago
2009
Tsinghua U.
Iterative stencil loops (ISLs) are used in many applications and tiling is a well-known technique to localize their computation. When ISLs are tiled across a parallel architecture...