111 search results - page 4 / 23 » Using Multiple Memory Access Instructions for Reducing Code ... |
CASES
2006
ACM
14 years 5 days ago
2006
ACM
The architectural design of embedded systems is becoming increasingly idiosyncratic to meet varying constraints regarding energy consumption, code size, and execution time. Tradit...
DAC
2004
ACM
14 years 7 months ago
2004
ACM
Code compression has been shown to be an effective technique to reduce code size in memory constrained embedded systems. It has also been used as a way to increase cache hit ratio...
PLDI
1995
ACM
13 years 9 months ago
1995
ACM
DSP architectures typically provide indirect addressing modes with auto-increment and decrement. In addition, indexing mode is not available, and there are usually few, if any, ge...
ICS
2005
Tsinghua U.
13 years 11 months ago
2005
Tsinghua U.
With the increasing performance gap between the processor and the memory, the importance of caches is increasing for high performance processors. However, with reducing feature si...
LCTRTS
2007
Springer
14 years 10 days ago
2007
Springer
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...