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» Using Negative Correlation to Evolve Fault-Tolerant Circuits
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AHS
2006
IEEE
113views Hardware» more  AHS 2006»
13 years 8 months ago
A Honeycomb Development Architecture for Robust Fault-Tolerant Design
A new hardware developmental model that shows strong robust transient fault-tolerant abilities and is motivated by embryonic development and a honeycomb structure is presented. Ca...
Andy M. Tyrrell, Hong Sun
STOC
1997
ACM
122views Algorithms» more  STOC 1997»
13 years 9 months ago
Fault-Tolerant Quantum Computation With Constant Error
Shor has showed how to perform fault tolerant quantum computation when the probability for an error in a qubit or a gate, η, decays with the size of the computation polylogarithmi...
Dorit Aharonov, Michael Ben-Or
DAC
2007
ACM
14 years 5 months ago
Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement
Negative bias temperature instability (NBTI) in MOSFETs is one of the major reliability challenges in nano-scale technology. This paper presents an efficient technique to characte...
Kunhyuk Kang, Kee-Jong Kim, Ahmad E. Islam, Muhamm...
GLVLSI
2008
IEEE
204views VLSI» more  GLVLSI 2008»
13 years 11 months ago
NBTI resilient circuits using adaptive body biasing
Reliability has become a practical concern in today’s VLSI design with advanced technologies. In-situ sensors have been proposed for reliability monitoring to provide advance wa...
Zhenyu Qi, Mircea R. Stan
SEDE
2007
13 years 6 months ago
Case study: A tool centric approach for fault avoidance in microchip designs
— Achieving reliability in fault tolerant systems requires both avoidance and redundancy. This study focuses on avoidance as it pertains to the design of microchips. The lifecycl...
Clemente Izurieta