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» Using Negative Correlation to Evolve Fault-Tolerant Circuits
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DATE
2010
IEEE
161views Hardware» more  DATE 2010»
13 years 10 months ago
Aging-resilient design of pipelined architectures using novel detection and correction circuits
—Time-dependent performance degradation due to transistor aging caused by mechanisms such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) is one o...
Hamed F. Dadgour, Kaustav Banerjee
IJCNN
2008
IEEE
13 years 12 months ago
On-line bagging Negative Correlation Learning
— Negative Correlation Learning (NCL) has been showing to outperform other ensemble learning approaches in off-line mode. A key point to the success of NCL is that the learning o...
Fernanda L. Minku, Xin Yao
GECCO
2006
Springer
137views Optimization» more  GECCO 2006»
13 years 9 months ago
Evolutionary design of fault-tolerant analog control for a piezoelectric pipe-crawling robot
In this paper, a genetic algorithm (GA) is used to design faulttolerant analog controllers for a piezoelectric micro-robot. Firstorder and second-order functions are developed to ...
Geoffrey A. Hollinger, David A. Gwaltney
FPGA
2009
ACM
159views FPGA» more  FPGA 2009»
14 years 10 days ago
Choose-your-own-adventure routing: lightweight load-time defect avoidance
Aggressive scaling increases the number of devices we can integrate per square millimeter but makes it increasingly difficult to guarantee that each device fabricated has the inte...
Raphael Rubin, André DeHon
DAC
2001
ACM
14 years 6 months ago
A True Single-Phase 8-bit Adiabatic Multiplier
This paper presents the design and evaluation of an 8-bit adiabatic multiplier. Both the multiplier core and its built-in self-test logic have been designed using a true single-ph...
Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthy...