17 search results - page 1 / 4 » Using Process-Level Redundancy to Exploit Multiple Cores for... |
DSN
2007
IEEE
13 years 11 months ago
2007
IEEE
Transient faults are emerging as a critical concern in the reliability of general-purpose microprocessors. As architectural trends point towards multi-threaded multi-core designs,...
DFT
2003
IEEE
13 years 10 months ago
2003
IEEE
This paper presents an approach for integrating fault-tolerance techniques into microprocessors by utilizing instruction redundancy as well as time redundancy. Smaller and smaller...
DSN
2007
IEEE
13 years 11 months ago
2007
IEEE
A new approach is proposed that exploits repetition inherent in programs to provide low-overhead transient fault protection in a processor. Programs repeatedly execute the same in...
EDCC
2008
Springer
13 years 6 months ago
2008
Springer
The ongoing technological advances in the semiconductor industry make Multi-Processor System-on-a-Chips (MPSoCs) more attractive, because uniprocessor solutions do not scale satis...
CLEIEJ
2006
13 years 4 months ago
2006
This paper describes a single-version algorithmic approach to design in fault tolerant computing in various computing systems by using static redundancy in order to mask transient...