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» Using RTL Statespace Information and State Encoding for Indu...
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DATE
2003
IEEE
66views Hardware» more  DATE 2003»
13 years 10 months ago
Using RTL Statespace Information and State Encoding for Induction Based Property Checking
This paper focuses on checking safety properties for sequential circuits specified on the RT-level. We study how different state encodings can be used to create a gate-level repr...
Markus Wedler, Dominik Stoffel, Wolfgang Kunz
KBSE
2005
IEEE
13 years 11 months ago
Learning to verify branching time properties
We present a new model checking algorithm for verifying computation tree logic (CTL) properties. Our technique is based on using language inference to learn the fixpoints necessar...
Abhay Vardhan, Mahesh Viswanathan
DATE
2004
IEEE
129views Hardware» more  DATE 2004»
13 years 9 months ago
On the Design and Verification Methodology of the Look-Aside Interface
In this paper, we present a technique to design and verify the Look-Aside (LA-1) Interface standard used in network processors. Our design flow includes several refinements starti...
Ali Habibi, Asif Iqbal Ahmed, Otmane Aït Moha...
CCS
2011
ACM
12 years 5 months ago
Automatic error finding in access-control policies
Verifying that access-control systems maintain desired security properties is recognized as an important problem in security. Enterprise access-control systems have grown to prote...
Karthick Jayaraman, Vijay Ganesh, Mahesh V. Tripun...