54 search results - page 11 / 11 » Using a Swap Instruction to Coalesce Loads and Stores |
ISCA
1995
IEEE
13 years 9 months ago
1995
IEEE
For many programs, especially integer codes, untolerated load instruction latencies account for a significant portion of total execution time. In this paper, we present the desig...
ISCA
2000
IEEE
13 years 9 months ago
2000
IEEE
Smaller feature sizes, reduced voltage levels, higher transistor counts, and reduced noise margins make future generations of microprocessors increasingly prone to transient hardw...
HIPC
1999
Springer
13 years 9 months ago
1999
Springer
We describe a radically new cache architecture and demonstrate that it offers a huge reduction in cache cost, size and power consumption whilst maintaining performance on a wide ra...
EIT
2008
IEEE
13 years 11 months ago
2008
IEEE
—The rapid growth and pervasive use of embedded systems makes it easier for an adversary to gain physical access to these devices to launch attacks and reverse engineer of the sy...