24 search results - page 2 / 5 » Using a User-Level Memory Thread for Correlation Prefetching |
ICS
2010
Tsinghua U.
13 years 6 months ago
2010
Tsinghua U.
Data prefetching technique is widely used to bridge the growing performance gap between processor and memory. Numerous prefetching techniques have been proposed to exploit data pa...
CCGRID
2001
IEEE
13 years 8 months ago
2001
IEEE
Though shared virtual memory (SVM) systems promise low cost solutions for high performance computing, they suffer from long memory latencies. These latencies are usually caused by...
IPPS
2003
IEEE
13 years 10 months ago
2003
IEEE
Concurrent multithreaded architectures exploit both instruction-level and thread-level parallelism through a combination of branch prediction and thread-level control speculation. ...
MICRO
2002
IEEE
13 years 9 months ago
2002
IEEE
Data prefetching effectively reduces the negative effects of long load latencies on the performance of modern processors. Hardware prefetchers employ hardware structures to predic...
IPPS
2009
IEEE
13 years 11 months ago
2009
IEEE
DTA (Decoupled Threaded Architecture) is designed to exploit fine/medium grained Thread Level Parallelism (TLP) by using a distributed hardware scheduling unit and relying on exi...