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ASPDAC
2004
ACM
129views Hardware» more  ASPDAC 2004»
13 years 10 months ago
Instruction buffering exploration for low energy VLIWs with instruction clusters
— For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the instruction memory of embedded processors. In particular, software controlled ...
Tom Vander Aa, Murali Jayapala, Francisco Barat, G...
QEST
2007
IEEE
13 years 11 months ago
A Petri Net Model for Evaluating Packet Buffering Strategies in a Network Processor
Previous studies have shown that buffering packets in DRAM is a performance bottleneck. In order to understand the impediments in accessing the DRAM, we developed a detailed Petri...
Girish B. C., R. Govindarajan
ASAP
2006
IEEE
134views Hardware» more  ASAP 2006»
13 years 7 months ago
Buffer and register allocation for memory space optimization
In today's embedded systems, memory hierarchy is rapidly becoming a major factor in terms of power, performance and area. This is especially true for embedded multimedia appl...
Youcef Bouchebaba, Gabriela Nicolescu, El Mostapha...
HPCA
2004
IEEE
14 years 5 months ago
Signature Buffer: Bridging Performance Gap between Registers and Caches
Data communications between producer instructions and consumer instructions through memory incur extra delays that degrade processor performance. In this paper, we introduce a new...
Lu Peng, Jih-Kwon Peir, Konrad Lai
ICDE
2003
IEEE
108views Database» more  ICDE 2003»
14 years 6 months ago
MEMS-based Disk Buffer for Streaming Media Servers
The performance of streaming media servers has been limited due to the dual requirements of high throughput and low memory use. Although disk throughput has been enjoying a 40% an...
Raju Rangaswami, Zoran Dimitrijevic, Edward Y. Cha...