262 search results - page 1 / 53 » Using dynamic cache management techniques to reduce energy i... |
ISLPED
1999
ACM
13 years 9 months ago
1999
ACM
In this paper, we propose a technique that uses an additional mini cache, the L0-Cache, located between the instruction cache I-Cache and the CPU core. This mechanism can provid...
PACS
2000
Springer
13 years 8 months ago
2000
Springer
Power dissipation is a major concern not only for portable systems, but also for high-performance systems. In the past, energy consumption and processor heating was reduced mainly...
MICRO
2003
IEEE
13 years 10 months ago
2003
IEEE
High-performance caches statically pull up the bitlines in all cache subarrays to optimize cache access latency. Unfortunately, such an architecture results in a significant wast...
CASES
2006
ACM
13 years 10 months ago
2006
ACM
Virtual caches are employed as L1 caches of both high performance and embedded processors to meet their short latency requirements. However, they also introduce the synonym proble...
PACS
2000
Springer
13 years 8 months ago
2000
Springer
Increasing power dissipation has become a major constraint for future performance gains in the design of microprocessors. In this paper, we present the circuit design of an issue ...