173 search results - page 35 / 35 » Using hardware transactional memory for data race detection |
IMC
2010
ACM
13 years 2 months ago
2010
ACM
Network management applications require accurate estimates of a wide range of flow-level traffic metrics. Given the inadequacy of current packet-sampling-based solutions, several ...
ISCA
2006
IEEE
13 years 11 months ago
2006
IEEE
Level one cache normally resides on a processor’s critical path, which determines the clock frequency. Directmapped caches exhibit fast access time but poor hit rates compared w...
ISCA
2002
IEEE
13 years 4 months ago
2002
IEEE
Traditional vector architectures have shown to be very effective for regular codes where the compiler can detect data-level parallelism. However, this SIMD parallelism is also pre...