8 search results - page 2 / 2 » Utilization of Cache Area in On-Chip Multiprocessor |
ISCA
2005
IEEE
13 years 11 months ago
2005
IEEE
With the ability to place large numbers of transistors on a single silicon chip, manufacturers have begun developing chip multiprocessors (CMPs) containing multiple processor core...
ISCA
2009
IEEE
14 years 20 hour ago
2009
IEEE
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
ISCA
2005
IEEE
13 years 11 months ago
2005
IEEE
It has been shown that many requests miss in all remote nodes in shared memory multiprocessors. We are motivated by the observation that this behavior extends to much coarser grai...