46 search results - page 2 / 10 » VERILAT: verification using logic augmentation and transform... |
POPL
2005
ACM
14 years 6 months ago
2005
ACM
We present Rhodium, a new language for writing compiler optimizations that can be automatically proved sound. Unlike our previous work on Cobalt, Rhodium expresses optimizations u...
VLSID
2002
IEEE
14 years 6 months ago
2002
IEEE
We propose the redundancy identification of wire replacement faults. The solutions rely on the satisfiability (SAT) formulation of redundancy identification, augmented with the me...
DAC
2005
ACM
13 years 7 months ago
2005
ACM
Parallelism in processor architecture and design imposes a verification challenge as the exponential growth in the number of execution combinations becomes unwieldy. In this paper...
JUCS
2006
13 years 5 months ago
2006
Abstract: We present a novel approach to the verification of functional-logic programs. For our verification purposes, equational reasoning is not valid due to the presence of non-...
TCS
2002
13 years 5 months ago
2002
We consider the timed automata model of [3], which allows the analysis of realtime systems expressed in terms of quantitative timing constraints. Traditional approaches to real-ti...