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GLVLSI
2007
IEEE
141views VLSI» more  GLVLSI 2007»
13 years 12 months ago
Transition-activity aware design of reduction-stages for parallel multipliers
We propose an interconnect reorganization algorithm for reduction stages in parallel multipliers. It aims at minimizing power consumption for given static probabilities at the pri...
Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Osc...
ICC
2007
IEEE
106views Communications» more  ICC 2007»
13 years 12 months ago
A Hierarchical Weighted Round Robin EPON DBA Scheme and Its Comparison with Cyclic Water-Filling Algorithm
—A H-WRR (Hierarchical Weighted Round-Robin) EPON (Ethernet Passive Optical Network) DBA (Dynamic Bandwidth Allocation) algorithm is devised and investigated. WRR table entries h...
Chan Kim, Tae-Whan Yoo, Bong-Tae Kim
DATE
2006
IEEE
123views Hardware» more  DATE 2006»
13 years 11 months ago
Networks on chips for high-end consumer-electronics TV system architectures
Consumer electronics products, such as high-end (digital) TVs, contain complex systems on chip (SOC) that offer high computational performance at low cost. Traditionally, these SO...
Frits Steenhof, Harry Duque, Björn Nilsson, K...
FCCM
2006
IEEE
133views VLSI» more  FCCM 2006»
13 years 11 months ago
A Field Programmable RFID Tag and Associated Design Flow
Current Radio Frequency Identification (RFID) systems generally have long design times and low tolerance to changes in specification. This paper describes a field programmable,...
Alex K. Jones, Raymond R. Hoare, Swapna R. Donthar...
LCTRTS
2005
Springer
13 years 11 months ago
Preventing interrupt overload
Performance guarantees can be given to tasks in an embedded system by ensuring that access to each shared resource is mediated by an appropriate scheduler. However, almost all pre...
John Regehr, Usit Duongsaa