5 search results - page 1 / 1 » VLSI Implementation of Fully Parallel LTE Turbo Decoders |
VTC
2008
IEEE
13 years 11 months ago
2008
IEEE
—The design of LTE turbo coding chain suitable for flexible parallel and pipelined hardware implementations is presented. The hierarchical data structure further offers an opport...
IEICET
2006
13 years 5 months ago
2006
ASAP
2011
IEEE
2011
IEEE
High-throughput Contention-Free concurrent interleaver architecture for multi-standard turbo decoder
12 years 5 months ago
—To meet the higher data rate requirement of emerging wireless communication technology, numerous parallel turbo decoder architectures have been developed. However, the interleav...
FCCM
2008
IEEE
13 years 11 months ago
2008
IEEE
We propose a new powerful scalable generic parallel and modular architecture well suited to LDPC code decoding. This architecture template has been instantiated in the case of the...
FCCM
2004
IEEE
13 years 8 months ago
2004
IEEE
We describe a flexible hardware encoder for regular and irregular low-density parity-check (LDPC) codes. Although LDPC codes achieve achieve better performance and lower decoding ...