25 search results - page 1 / 5 » VLSI Layout of Benes Networks |
FCS
2006
13 years 6 months ago
2006
IPPS
1999
IEEE
13 years 9 months ago
1999
IEEE
We propose the recursive grid layout scheme for deriving efficient layouts of a variety of hierarchical networks and computing upper bounds on the VLSI area of general hierarchica...
ICPP
2000
IEEE
13 years 9 months ago
2000
IEEE
Current VLSI technology allows more than two wiring layers and the number is expected to rise in future. In this paper, we show that, by designing VLSI layouts directly for an L-l...
APCCAS
2002
IEEE
13 years 10 months ago
2002
IEEE
The pyramid networks are well-known as suitable structures for parallel computations such as image processing. This paper shows a practical 3D VLSI layout of the N-vertex pyramid ...
DAC
1999
ACM
14 years 5 months ago
1999
ACM
We propose a new VLSI layout methodology which addresses the main problems faced in Deep Sub-Micron (DSM) integrated circuit design. Our layout "fabric" scheme eliminate...