25 search results - page 3 / 5 » VLSI Layout of Benes Networks |
JOIN
2007
13 years 5 months ago
2007
In VLSI layout of interconnection networks, routing two-point nets in some restricted area is one of the central operations. It aims usually to minimize the layout area, while red...
ARVLSI
1997
IEEE
13 years 10 months ago
1997
IEEE
This paper describes the architecture and implementation of a high-speed decompression engine for embedded processors. The engine is targeted to processors where embedded programs...
DFT
2006
IEEE
13 years 9 months ago
2006
IEEE
The concept of clocking for QCA, referred to as the four-phase clocking, is widely used. However, inherited characteristics of QCA, such as the way to hold state, the way to synch...
JPDC
2006
13 years 5 months ago
2006
Minimum Spanning Tree (MST) is one of the most studied combinatorial problems with practical applications in VLSI layout, wireless communication, and distributed networks, recent ...
ICPP
1994
IEEE
13 years 10 months ago
1994
IEEE
Recently, the mesh connected trees (MCT) network has been proposed as a possible architecture for parallel computers. MCT networks are obtained by combining complete binary trees ...