92 search results - page 3 / 19 » VLSI architecture based on packet data transfer scheme and i... |
ICPP
2006
IEEE
13 years 11 months ago
2006
IEEE
— This paper focuses on the transfer of large data in SMP systems. Achieving good performance for intranode communication is critical for developing an efficient communication s...
ISCAS
1994
IEEE
13 years 9 months ago
1994
IEEE
This paper presents a novel VLSI architecture for high-speed data compressor designs which implement the well-known LZ77 algorithm. The architecture mainly consists of three units...
HPCA
2009
IEEE
14 years 5 months ago
2009
IEEE
Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core architectures. To reduce th...
ICDCS
2010
IEEE
13 years 7 months ago
2010
IEEE
Due to the lack of multicast services in the Internet, applications based on single source multiple destinations transfers such as video conferencing, IP radio, IPTV must use unica...
TON
2002
13 years 5 months ago
2002
Abstract--Research on congestion-control algorithms has traditionally focused more on performance than on robustness of the closed-loop system to changes in network conditions. As ...