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» Validating High-Level Synthesis
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DAC
1992
ACM
13 years 9 months ago
High Level Synthesis of Pipelined Instruction Set Processors and Back-End Compilers
Designing instruction set processors and constructing their compilers are mutually dependent tasks. Piper is a high level synthesis tool of ADAS which controls the hardware-softwa...
Ing-Jer Huang, Alvin M. Despain
DATE
2008
IEEE
116views Hardware» more  DATE 2008»
13 years 11 months ago
A Variation Aware High Level Synthesis Framework
— The worst-case delay/power of function units has been used in traditional high level synthesis to facilitate design space exploration. As technology scales to nanometer regime,...
Feng Wang 0004, Guangyu Sun, Yuan Xie
DATE
1998
IEEE
109views Hardware» more  DATE 1998»
13 years 9 months ago
Cross-Level Hierarchical High-Level Synthesis
This paper presents a new approach to cross-level hierarchical high-level synthesis. A methodology is presented, that supports the efficient synthesis of hierarchical specified sy...
Oliver Bringmann, Wolfgang Rosenstiel
VLSID
2002
IEEE
105views VLSI» more  VLSID 2002»
14 years 5 months ago
A Heuristic for Clock Selection in High-Level Synthesis
Clock selection has a significant impact on the performance and quality of designs in high-level synthesis. In most synthesis systems, a convenient value of the clock is chosen or...
J. Ramanujam, Sandeep Deshpande, Jinpyo Hong, Mahm...
WSC
2001
13 years 6 months ago
Production scheduling validity in high level supply chain models
Although they focus on the big picture, high level supply chain models cannot gloss over the capacity of production nodes to meet production allocations. Capacity is not simply a ...
David J. Parsons, Richard A. Phelps