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DAC
1992
ACM

High Level Synthesis of Pipelined Instruction Set Processors and Back-End Compilers

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High Level Synthesis of Pipelined Instruction Set Processors and Back-End Compilers
Designing instruction set processors and constructing their compilers are mutually dependent tasks. Piper is a high level synthesis tool of ADAS which controls the hardware-software interactions at the micro-architecture level. The key function of Piper is to perform pipeline scheduling with any fixed instructionlatency, and generate a reorder table for a back-end compiler to resolve potential pipeline hazards existing in the design. Models for performance and cost of both hardware and software are developed in order to characterize the design space. A synthesis example of a simple instruction set processor illustrates Piper's synthesis capabilities and how the performance and cost of hardware and software are estimated.
Ing-Jer Huang, Alvin M. Despain
Added 10 Aug 2010
Updated 10 Aug 2010
Type Conference
Year 1992
Where DAC
Authors Ing-Jer Huang, Alvin M. Despain
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