High Level Synthesis of Pipelined Instruction Set Processors and Back-End Compilers

Designing instruction set processors and constructing their compilers are mutually dependent tasks. Piper is a high level synthesis tool of ADAS which controls the hardware-software interactions at the micro-architecture level. The key function of Piper is to perform pipeline scheduling with any fixed instructionlatency, and generate a reorder table for a back-end compiler to resolve potential pipeline hazards existing in the design. Models for performance and cost of both hardware and software are developed in order to characterize the design space. A synthesis example of a simple instruction set processor illustrates Piper's synthesis capabilities and how the performance and cost of hardware and software are estimated.

• Type: Conference
• Year: 1992
• Where: DAC
• Authors: Ing-Jer Huang, Alvin M. Despain
• Keywords: Computer Architecture, DAC 1992, Instruction Set Processor, Level Synthesis Tool, Piper's Synthesis Capabilities