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CHES
2011
Springer
276views Cryptology» more  CHES 2011»
12 years 4 months ago
FPGA-Based True Random Number Generation Using Circuit Metastability with Adaptive Feedback Control
Abstract. The paper presents a novel and efficient method to generate true random numbers on FPGAs by inducing metastability in bi-stable circuit elements, e.g. flip-flops. Meta...
Mehrdad Majzoobi, Farinaz Koushanfar, Srinivas Dev...
ESSCIRC
2011
93views more  ESSCIRC 2011»
12 years 4 months ago
12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 volta
— Within-functional-block fine-grained adaptive dual supply voltage control (FADVC) is proposed to reduce the power of CMOS logic circuits. Both process and design variations wi...
Atsushi Muramatsu, Tadashi Yasufuku, Masahiro Nomu...
IJON
2007
118views more  IJON 2007»
13 years 4 months ago
Low power CMOS electronic central pattern generator design for a biomimetic underwater robot
— This paper, presents a feasability study of a central pattern generator-based analog controller for an autonomous robot. The operation of a neuronal circuit formed of electroni...
Young-Jun Lee, Jihyun Lee, Kyung Ki Kim, Yong-Bin ...
DAC
2006
ACM
14 years 5 months ago
Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM
Increasing source voltage (Source-Biasing) is an efficient technique for reducing gate and sub-threshold leakage of SRAM arrays. However, due to process variation, a higher source...
Swaroop Ghosh, Saibal Mukhopadhyay, Kee-Jong Kim, ...
PATMOS
2007
Springer
13 years 11 months ago
Soft Error-Aware Power Optimization Using Gate Sizing
—Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the...
Foad Dabiri, Ani Nahapetian, Miodrag Potkonjak, Ma...